Delay Reducing Design for 2- bit Reversible Comparator Unit

Abstract

On earth, communication between any organisms is in the form of an analog signal. The manipulation of an analog signal is tedious; therefore analog to digital converter is used to convert the analog signal into digital form. Comparator plays a major role in the signal analysis. In addition to that, comparator circuit provides the efficient and high quality signal, among, the various input signals fed as an input. Magnitude comparator is a technique used to compare, the relation between given inputs in digital form that is in the form of 1’s and 0’s. Comparison between one or more input signals can be generated by using the relational operators. A comparison using conventional method is less immune to the noise; is a well-known aspect.  Taking into an account, the reversible logic gates, which has zero loss of information is used to perform the comparison of two bit input data. In this paper, a comparison is made between the two bit input data. The relative results such as A>B, A<B, A=B are provided for any 2 bit input combinations.  The proposed reversible 2-bit comparator module effectively reduces the number of gates used, garbage values and the delay. The delay for reversible 2 bit comparator unit is 6.320 ns. The proposed architecture for the 2-bit reversible comparator using various reversible gates is provided with the output simulated using “ModelSim” and the synthesis report is generated using “Xilinx”.